The present invention relates, in general, to the field of microprocessors (MPUs) and microcomputers (MCUs). More particularly, the present invention relates to a wait mode power reduction system and method for a data processor which allows for the shutting down of a data processor subsystem, for example, a timer system, if an interrupt is impossible from that subsystem.
During a data processor wait mode, processing by the CPU is suspended. Thus, no changes can occur to the data processor condition code register (CCR) or the computer operating properly (COP) watchdog timer system, if utilized. In a stop mode, minimum power consumption is effectuated in a data processor because all clocks including the crystal oscillator are stopped while in this mode. Similarly, in the wait mode, while processing is also suspended, portions of a data processor's subsystems may be shut down during this mode to effectuate a power consumption savings. However, if significant circuitry were required to determine the subsystem's ability or inability to be shut down, the savings in the wait mode power would be obviated by the cost in on-chip area and circuit complexity. In CMOS circuitry, power consumption is virtually all due to signal transitions of the various device nodes. Therefore, if the clocks to the data processor subsystem are stopped, power consumption is reduced to an absolute minimum.
By determining a subsystem's ability or inability to produce an interrupt, it is possible for a data processor's subsystems to be shut down, thus effectuating a power savings.